Encoding:

Format:

SHRA[_R].QB 

SHRA.QB    rdt, rts, sa

SHRA_R.QB  rdt, rts, sa

Purpose:

Shift Right Arithmetic Vector of Four Bytes

To execute an arithmetic right shift on four independent bytes by a fixed number of bits.

Description:

rdt = sign_extend(round(rts31..24 >> sa) || round(rts23..16 >> sa) || round(rts15..8 >> sa) || round(rts7..0 >> sa))

The four right-most byte elements in register rts are each shifted right arithmetically by sa bits, then written to the corresponding vector elements in destination register rdt. The sa argument is interpreted as an unsigned three-bit integer taking values from zero to seven.

In the rounding variant of the instruction, a value of 1 is added at th e most significant discarded bit position of each result prior to writing the rounded result to the destination register.

The sign of the left-most byte result is extended into the 32 most-significant bits of the destination register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

SHRA.QB:
   tempD7..0 = ( GPR[rts]31)sa || GPR[rts]31..24+sa )
   tempC7..0 = ( GPR[rts]23)sa || GPR[rts]23..16+sa )
   tempB7..0 = ( GPR[rts]15)sa || GPR[rts]15..8+sa )
   tempA7..0 = ( GPR[rts]7)sa || GPR[rts]7..sa )
   GPR[rdt]63..0 = (tempD7)32 || tempD7..0 || tempC7..0 || tempB7..0 || tempA7..0
SHRA_R.QB:
   if ( sa2..0 = 0 ) then
      tempD7..0 = GPR[rts]31..24
      tempC7..0 = GPR[rts]23..16
      tempB7..0 = GPR[rts]15..8
      tempA7..0 = GPR[rts]7..0
   else
      tempD8..0 = ( GPR[rts]31)sa || GPR[rts]31..24+sa-1 ) + 1
      tempC8..0 = ( GPR[rts]23)sa || GPR[rts]23..16+sa-1 ) + 1
      tempB8..0 = ( GPR[rts]15)sa || GPR[rts]15..8+sa-1 ) + 1
      tempA8..0 = ( GPR[rts]7)sa || GPR[rts]7..sa-1 ) + 1
   endif
   GPR[rdt]63..0 = (tempD8)32 || tempD8..1 || tempC8..1 || tempB8..1 || tempA8..1

Exceptions:

Reserved Instruction, DSP Disabled